Serial interfaces are widely employed in digital applications to send and receive digital data between different components of a digital system. As a typical example, various serial interface standards, such as USB2.0, serial ATA and PCI express, have been adopted to provide wireline chip-to-chip communication between modules in a personal computer. While the trend of developing larger, faster, more complex digital system continues, e.g., multi-medium personal computers capable of processing larger amount to digital data in real time, serial interface technology is quickly evolving to cope with the trend. As a consequence, serial interfaces adopted in advanced digital system generally should exhibit the following desirable characteristics: higher processing speed, processing digital signals with reduced signal amplitudes, increased noise tolerance, reduced power consumption, dynamic adjustment of input bandwidth, and dynamic adjustment of envelope level, among others.
FIG. 1 is a system diagram illustrating a conventional envelope detecting circuit provided in an existing serial interface for detecting digital signals in a chip-to-chip communication channel. Digital signals transmitted through the communication channel are generally in the form of signal packets modulated on a carrier frequency. The packets are detected from the communication channel through the potential difference between input differential signals Vin+ and Vin−. For example, when the potential difference between Vin+ and Vin− is below a pre-determined offset reference value, the communication channel is in a non-signal state; when the difference between Vin+ and Vin− is above the pre-determined offset reference value, the communication channel is in a signal state. A signal packet is identified by the envelope detecting circuit, which proceeds to process and extract the desired envelope signal from the packet.
The envelope detecting circuit includes a first differential operational amplifier that receives input differential signals Vin+ and Vin− and amplifies the positive-side magnitude of an incoming waveform and outputs to a gain stage. The envelope detecting circuit also includes a second differential operational amplifier that receives input differential signals Vin+ and Vin− and amplifies the negative-side magnitude of an incoming waveform and outputs to a gain stage. A potential hold circuit holds the potential from the gain stages. A comparator circuit compares the potential held by the potential hold circuit with the pre-determined offset reference value to decide whether there is a signal or non-signal state and outputs the result as a detect signal.
While high-speed signal transfer in an advanced digital system becomes increasingly important, the operation of the conventional envelope detecting circuit described above is problematic in a number of ways. First, the conventional envelope detecting circuit requires multiple operational amplifiers and consumes significant power. Furthermore, the plural operational amplifiers presented at the front stage of a conventional envelope detecting circuit exhibit a large input capacitance load, which generally limits the speed of signal receiving and sending. In addition, the conventional envelope detecting circuit lacks the capability of input signal bandwidth selection and dynamic envelope level tuning, which would be desirable in advanced high-speed digital system.